ARBCMDSRC=ARBCMDSRC_0
Status Register 0
| SEQIDLE | This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface. |
| ARBIDLE | This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. |
| ARBCMDSRC | This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). 0 (ARBCMDSRC_0): Triggered by AHB read command (triggered by AHB read). 1 (ARBCMDSRC_1): Triggered by AHB write command (triggered by AHB Write). 2 (ARBCMDSRC_2): Triggered by IP command (triggered by setting register bit IPCMD.TRG). 3 (ARBCMDSRC_3): Triggered by suspended command (resumed). |